may 2007 rev 1 1/8 AN2551 application note configuring the str91xfa mcu for optimum cpu performance introduction the str91xfa series of flash mcus is based on an arm966e cpu core which executes code directly from its in ternal flash memory at a rate of up to 96 mhz. to allow flexibility for a variety of applications and power management schemes, there are many configuration settings available to firmware during the initialization of the str91xfa at start-up. this application note outlines the necessary steps to ensure the str91xfa is configured for optimum performance for those applications which require the str91xfa to operate at full speed and deliver the highest performance from the cpu core and highest bandwidth of data movement. the related software is packed into a zip file associated with this application note and available from http://www.st.com/. www.st.com
contents AN2551 2/8 contents 1 about str91xfa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 configuring str91xfa for best performance . . . . . . . . . . . . . . . . . . . . 4 2.1 system clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 wait states insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 buffered writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 pre-fetch queue (pfq), branch cache (bc) accelerator . . . . . . . . . . . . . 5 2.5 instruction-set mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AN2551 about str91xfa 3/8 1 about str91xfa the str91xfa family of mcus combines a powerful 32-bit arm966e risc processor core, dual-bank flash memory reaching 544 kbytes and a vast 96 kbyte sram for data or code storage. it includes a rich peripheral set to form an ideal embedded controller for a wide variety of applications. this microcontroller has a custom memory accelerator, consisting of a pre-fetch unit and branch cache coupled with the instruction tightly coupled memory (i-tcm) of the cpu core, to accelerate the performance of the flash memory system and lower interrupt latency. the job of the pfq is to keep the arm core continuously fed with instructions. it performs asynchronous pre-fetch cycles to the flash memory during idle bus cycles to keep the pre-fetch queue full. when instruction addresses are sequential, the burst flash memory will supply the cpu core with 32-bit inst ructions at a continuo us rate of 96 mhz. however, when instructions have non-sequential addresses, such as during a branch in code execution, the pf q must be flushed and refilled, which imposes a stall to the cpu core. the role of the bc is to minimize the occurrences of these stalls. the bc will remember the first eight 32-bit instructions of each of the previous 15 branch destinations taken by the firmware. anytime one of thes e 15 branches is taken again, the bc will immediately supply the first eight instructions to the pfq, which significantly reduces the amount of time the cpu is stalled. while the cpu consumes these first eight instructions, the pfq has a chance to refill itself and be re ady to supply instructions again at 96 mhz on the 9th instruction. in order to take full advantage of the memory accelerator, th e system configuration registers of the str91xfa must be initialized correctly. for more about str91xfa, refer to http://www.st.com.
configuring str91xfa for best performance AN2551 4/8 2 configuring str91xfa for best performance the following items must be configured as indicated to achieve optimum cpu performance: 2.1 system clock configuration 1. the system clock can be boosted using the pll to 96 mhz by updating the pll configuration register scu_pllconf register. this clock is generated for internal use by selecting the appropria te multiplier and divider. 2. select the appropriate clock dividers in the clock control register (scu_clkcntr): a) the flash memory interface clock (fmiclk) should have the same frequency as the rclk clock (96 mhz) this means no fm iclk dividers used. as a result since flash has a sequential burst read up to 96 mhz, we reduce execution time from there. b) if code is executed from an external memory, it?s recommended that the external memory interface clock (bclk) to be used in its highest frequency depending on read access time of the external memory. c) for correct operation, the apb peripheral clock (pclk) frequ ency should be less than or equal to 48 mhz. so, to run apb bus at its maximum frequency, choose 2 as the pclk divider. 2.2 wait states insertion maximum memory performance is achieved by specifying the correct number of wait states in relation to the cpu and fmi operating frequency. 1. wait states may be specified for non-sequential-address read accesses of flash memory (no wait states are required for sequential-address read requests). for best performance, specify in the flash configuration register, bits 11 and 12 (see str9 flash programming manual), one wait state for an fmi frequency of 66 mhz or less, and 2 wait states when fmi frequency is above 66 mhz. 2. wait states may be specified for writin g flash memory. best performance is achieved when 1-cycle writes (zero wait states) are specified for flash write operations in the fmi control register, fmi_cr, bit 8 (see str91xfa reference manual). 3. wait states may be specified for accessing the sram from either the cpu's data tightly coupled interface (dtcm) or from the ahb bus. the dtcm and the ahb both share access to the sram through the sram arbiter circuitry. best performance is achieved when zero wait states are specified for sram access in the system configuration register0, scu_scr0 (see str91xf reference manual), bit 1 for dtcm access, and bit 2 for ahb access. 2.3 buffered writes the cpu can access sram and the peripherals on the ahb/apb using either buffered or non-buffered writes. buffered writes operations are implemented by writing to sram and peripherals in one address range, or standard non-buffered writes are implemented by writing to sram and peripherals at a different address range (see str91xfa datasheet for
AN2551 configuring str91xfa for best performance 5/8 memory map). when the cpu makes a buffered write operation through the dtcm to the sram, there will be zero delay, even if sram arbi tration is currently gr anted to the ahb at the time of the dtcm write operation. a simila r benefit can be enjoyed when the cpu writes to the peripheral on the ahb/apb, decoupling the cpu from waits associated with a busy bus or peripheral. however, care must be taken using buffered writes to preserve data coherency. for example, if the ahb has just written a value to sram while a buffered write is pending from the dtcm for the very same sram address, then when arbitration is granted to back the dtcm, the most current value ju st written by the ahb will be overwritten by the dtcm. if this situation would cause a problem in your system, then non buffered writes are required. 2.4 pre-fetch queue (pfq), br anch cache (bc) accelerator the pfq/bc memory accelerator can be enabled and disabled by firmware. by default, the pfq/bc is enabled, but it's important to ensu re that your initialization firmware has not disabled the pfq/bc unintentionally (bit0 of register scu_scr0). early versions of str91x firmware library from st contained a mistake in the initialization code which disabled the pfq/bc. additionally, in the first versio n of production silicon, str91xf (revd), the depth of the pfq is set to four instructions by default, and firmware must write to bit 0 of the fmi control register fmi_cr to specify a pfq depth of 8 instructions to achieve optimum cpu performance. however, in the current producti on silicon str91xfa (rev g), the depth of the pfq is fixed at eight instructions and it cannot be changed, ensuring optimum performance. 2.5 instruction-set mode 32-bit architectures have a higher performance when manipulating 32-bit data. for applications needing best performance, str91xfa should be used in arm (32-bit) mode.
implementation AN2551 6/8 3 implementation the guidelines given above could be implemented in ?c? code or even in the assembly startup file. the current application note provides a special assembly startup file "91x_init.s" for ewarm, rvdk, ride and rvmdk tools chain which covers all these guidelines. this start-up file configures the pll@96 mhz to be the default clock source. it offers also the ability to select either the osc clock or the rtc clock. the zip file associated with this application note contains: the str91x firmware library v1.2 from st (source and header files). a standard template project program that compiles all library files and also all the user modifiable files needed to create a new project: ? 91x_conf.h: the configuration header file with all peripherals defined by default. ? 91x_it.c: the source file containing the interrupt handlers (the function bodies are empty in this template). ? main.c: the main program body. ? ewarm, rvdk, ride, rvmdk sub-directories for each toolchain and contains the modified start-up file "91x_init.s" when booting from bank1 : use osc as the default clock source. if you want to run the cpu @ 66 mhz or higher, the pll configuration can be done in the application code (?c? code) instead of in the start-up assembly file. the flash wait state selection instructions must be executed from sram as it is not possible to read while wr iting in the same bank.
AN2551 revision history 7/8 4 revision history table 1. document revision history date revision changes 29-05-2007 1 initial release.
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